Johnson Counter ( Verilog ) with Test Fixture

Test Fixture Program :-

module tf_johnson_vlog;

// Inputs
reg clk;
reg reset;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)
Johnson_vlog uut (
.out(out),
.clk(clk),
.reset(reset)
);

initial begin
  clk=1'b1;
  forever #5 clk=~clk;
 end


 initial begin
  reset = 1;#10;
  reset = 1;#10;
  reset = 0;#30;
 end

endmodule

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Program for Johnson Counter (  VERILOG  ) :-

module Johnson_vlog(
 out      ,  // Output of the counter
 clk      ,  // clock input
 reset       // reset input
 );
 //----------Output Ports--------------
  output [3:0] out;
  //------------Input Ports--------------
  input clk, reset;
  //------------Internal Variables--------
  reg [3:0] out;
  //-------------Code Starts Here-------
  always @(posedge clk)
 if (reset)
  begin // active high reset
   out <= 3'b0000 ;
  end
 else
  begin
   out = {out[2:0],~out[3]};
  end

  endmodule