Two Bit Comparator Using Single Bit Comparator (Structoral)

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_comp_2_bit IS
END tb_comp_2_bit;

ARCHITECTURE behavior OF tb_comp_2_bit IS

    COMPONENT comp_2_bit
    PORT(
         a1 : IN  std_logic;
         a0 : IN  std_logic;
         b1 : IN  std_logic;
         b0 : IN  std_logic;
         l : OUT  std_logic;
         e : OUT  std_logic;
         g : OUT  std_logic
        );
    END COMPONENT;
 

   --Inputs
   signal a1 : std_logic := '0';
   signal a0 : std_logic := '0';
   signal b1 : std_logic := '0';
   signal b0 : std_logic := '0';

  --Outputs
   signal l : std_logic;
   signal e : std_logic;
   signal g : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: comp_2_bit PORT MAP (
          a1 => a1,
          a0 => a0,
          b1 => b1,
          b0 => b0,
          l => l,
          e => e,
          g => g
        );


   stim_proc: process
   begin
   
a1<='0';a0<='0';b1<='0';b0<='0';wait for 100 ns;
a1<='0';a0<='0';b1<='0';b0<='1';wait for 100 ns;
a1<='0';a0<='0';b1<='1';b0<='0';wait for 100 ns;
a1<='0';a0<='0';b1<='1';b0<='1';wait for 100 ns;
a1<='0';a0<='1';b1<='0';b0<='0';wait for 100 ns;
a1<='0';a0<='1';b1<='0';b0<='1';wait for 100 ns;
a1<='0';a0<='1';b1<='1';b0<='0';wait for 100 ns;
a1<='0';a0<='1';b1<='1';b0<='1';wait for 100 ns;
a1<='1';a0<='0';b1<='0';b0<='0';wait for 100 ns;
a1<='1';a0<='0';b1<='0';b0<='1';wait for 100 ns;
a1<='1';a0<='0';b1<='1';b0<='0';wait for 100 ns;
a1<='1';a0<='0';b1<='1';b0<='1';wait for 100 ns;
a1<='1';a0<='1';b1<='0';b0<='0';wait for 100 ns;
a1<='1';a0<='1';b1<='0';b0<='1';wait for 100 ns;
a1<='1';a0<='1';b1<='1';b0<='0';wait for 100 ns;
a1<='1';a0<='1';b1<='1';b0<='1';wait for 100 ns;

      wait;
   end process;

END;


--------------------------------------------------------------------------------------------------------------------------

Two Bit Comparator Structoral (  VHDL  )  :-

library ieee;
use ieee.std_logic_1164.all;

entity comp_2_bit is
port(a1,a0,b1,b0:in std_logic;
l,e,g:out std_logic);
end comp_2_bit;

architecture structure of comp_2_bit is
component comp_1_bit is
port(a,b:in std_logic;
l,e,g:out std_logic);
end component;
component and_2 is
port(a,b:in std_logic;
c:out std_logic);
end component;
component or_2 is
port(a,b:in std_logic;
c:out std_logic);
end component;
component nor_2 is
port(a,b:in std_logic;
c:out std_logic);
end component;
signal s1,s2,s3,e1,e0,l1,l0,g1,g0:std_logic;
begin
u1: comp_1_bit port map(a1,b1,l1,e1,g1);
u2: comp_1_bit port map(a0,b0,l0,e0,g0);
u3: and_2 port map(e1,e0,e);
u31: and_2 port map(e1,e0,s2);
u4: and_2 port map(e1,l0,s1);
u5: or_2 port map(l1,s1,l);
u51: or_2 port map(l1,s1,s3);
u6: nor_2 port map(s2,s3,g);
end structure;

Sub Program Single Bit Comparator:-

library ieee;
use ieee.std_logic_1164.all;

entity comp_1_bit is
 port(a,b:in std_logic;
   l,e,g:out std_logic);
end comp_1_bit;

architecture dataflow of comp_1_bit is
begin
l<='1' when a<b else '0';
e<='1' when a=b else '0';
g<='1' when a>b else '0';
end dataflow;