Tristate Buffer ( VHDL ) with Test Bench

Test Bench Program :-

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_t_buf IS
END tb_t_buf;

ARCHITECTURE behavior OF tb_t_buf IS

    COMPONENT t_buf
    PORT(
         c : IN  std_logic;
         a : IN  std_logic;
         y : OUT  std_logic
        );
    END COMPONENT;
 

   --Inputs
   signal c : std_logic := '0';
   signal a : std_logic := '0';

  --Outputs
   signal y : std_logic;


BEGIN
   uut: t_buf PORT MAP (
          c => c,
          a => a,
          y => y
        );


   stim_proc: process
   begin
      c<='0';a<='0';wait for 100 ns;
      c<='0';a<='1';wait for 100 ns;
      c<='1';a<='0';wait for 100 ns;
      c<='1';a<='1';wait for 100 ns;
      wait;
   end process;

END;



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Program for TRISTATE BUFFER (  VHDL  ) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity t_buf is
    Port ( c,a : in  STD_LOGIC;
           y : out  STD_LOGIC:='0');
end t_buf;

architecture Behavioral  of t_buf is
begin
process(c,a)
begin
if c='0' then
y<='Z';
else
y<=a;
end if;
end process;
end Behavioral;