Decoder ( VERILOG ) with Test Fixture ( Another Logic )

Decoder In another logic... ...

Test Fixture Program :-

module tf_Decoder_vlog11;

// Inputs
reg e;
reg a;
reg b;

// Outputs
wire firstout;
wire secondout;
wire thirdout;
wire fourthout;

// Instantiate the Unit Under Test (UUT)
Decoder_vlog11 uut (
.e(e),
.a(a),
.b(b),
.firstout(firstout),
.secondout(secondout),
.thirdout(thirdout),
.fourthout(fourthout)
);

initial begin
// Initialize Inputs
e = 0; a = 0; b = 0; #100;
e = 1; a = 0; b = 0; #100;
e = 1; a = 0; b = 1; #100;
e = 1; a = 1; b = 0; #100;
e = 1; a = 1; b = 1; #100;

end
   
endmodule



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Program for DECODER (  VERILOG  ) :-

module Decoder_vlog11( input e,
  input a, input b,
      output firstout,
  output secondout,
  output thirdout,
  output fourthout);

assign firstout = (e) ;
assign secondout = (e & (a | b)) ;
assign thirdout = (e & a) ;
assign fourthout = (e & a & b) ;
endmodule