Number of '1' in Given Number (Structural)

Main Program:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ones is

 Port ( x : in STD_LOGIC_VECTOR (7 downto 0);

 y : out STD_LOGIC_VECTOR (3 downto 0));

end ones;

architecture Behavioral of ones is

component coder is

Port ( a : in STD_LOGIC;

 b : in STD_LOGIC;

 c : in STD_LOGIC;

 d : in STD_LOGIC;

 q : out STD_LOGIC_VECTOR (2 downto 0));

end component;

component addr is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

 b : in STD_LOGIC_VECTOR (2 downto 0);

 s : out STD_LOGIC_VECTOR (3 downto 0));

end component;

signal l,m:std_logic_vector (2 downto 0);

begin

u1: coder port map(x(0),x(1),x(2),x(3),l);

u2: coder port map(x(4),x(5),x(6),x(7),m);

u3: addr port map(l,m,y);

end Behavioral;


Sub Program 1(4:3 Coder):-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity coder is

 Port ( a : in STD_LOGIC:='0';

 b : in STD_LOGIC:='0';

 c : in STD_LOGIC:='0';

 d : in STD_LOGIC:='0';

 q : out STD_LOGIC_VECTOR (2 downto 0));

end coder;

architecture Behavioral of coder is

begin

process(a,b,c,d)

begin

if a='0' and b='0' and c='0' and d='0' then q<="000";

elsif a='0' and b='0' and c='0' and d='1' then q<="001";

elsif a='0' and b='0' and c='1' and d='0' then q<="001";

elsif a='0' and b='0' and c='1' and d='1' then q<="010";

elsif a='0' and b='1' and c='0' and d='0' then q<="001";

elsif a='0' and b='1' and c='0' and d='1' then q<="010";

elsif a='0' and b='1' and c='1' and d='0' then q<="010";

elsif a='0' and b='1' and c='1' and d='1' then q<="011";

elsif a='1' and b='0' and c='0' and d='0' then q<="001";

elsif a='1' and b='0' and c='0' and d='1' then q<="010";

elsif a='1' and b='0' and c='1' and d='0' then q<="010";

elsif a='1' and b='0' and c='1' and d='1' then q<="011";

elsif a='1' and b='1' and c='0' and d='0' then q<="010";

elsif a='1' and b='1' and c='0' and d='1' then q<="011";

elsif a='1' and b='1' and c='1' and d='0' then q<="011";

elsif a='1' and b='1' and c='1' and d='1' then q<="100";

else q<="000";

end if;

end process;

end Behavioral;


Sub Program 2(Adder):-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity addr is

 Port ( a : in STD_LOGIC_VECTOR (2 downto 0):="000";

 b : in STD_LOGIC_VECTOR (2 downto 0):="000";

 s : out STD_LOGIC_VECTOR (3 downto 0));

end addr;

architecture Behavioral of addr is

begin

process(a,b)

begin

s<= ('0'&a) + ('0'&b);

end process;

end Behavioral;