Full Subtractor using Full Adder and Inverter (Structural)

Main program:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fs_use_fs is
    Port ( a : in  STD_LOGIC;
           bin : in  STD_LOGIC;
           c : in  STD_LOGIC;
           d : out  STD_LOGIC;
           bout : out  STD_LOGIC);
end fs_use_fs;

architecture Structural of fs_use_fs is
component fa
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           c : out  STD_LOGIC);
end component;
component not_1
    Port ( a : in  STD_LOGIC;
           b : out  STD_LOGIC);
end component;
signal not_a,not_d:std_logic;
begin
u1:not_1 port map(a,not_a);
u2:fa port map(not_a,bin,c,not_d,bout);
u3:not_1 port map(not_d,d);
end Structural;

Sub Program:-

Fulladder:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fa is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           cin : in  STD_LOGIC;
           s : out  STD_LOGIC;
           c : out  STD_LOGIC);
end fa;

architecture Dataflow of fa is

begin
s<=a xor b xor cin;
c<=(a and (b xor cin)) or (b and cin);
end Dataflow;


Not:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity not_1 is
    Port ( a : in  STD_LOGIC;
           b : out  STD_LOGIC);
end not_1;

architecture Dataflow of not_1 is

begin
b<= not a;
end Dataflow;