Half adder / Half subtractor using 2:1 mux only (Structural)

Main Program:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HA_HS is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           m : in  STD_LOGIC;
           s_d : out  STD_LOGIC;
           c_b : out  STD_LOGIC);
end HA_HS;

architecture Structoral of HA_HS is

component mux_2_1
Port ( a0 : in  STD_LOGIC;
           a1 : in  STD_LOGIC;
           s : in  STD_LOGIC;
           y : out  STD_LOGIC);
end component;

signal s:std_logic_vector(0 to 1);

begin
u1:mux_2_1 port map('1','0',a,s(0)); --complement of a is s(0)
u2:mux_2_1 port map(a,s(0),b,s_d);
u3:mux_2_1 port map(a,s(0),m,s(1));
u4:mux_2_1 port map('0',s(1),b,c_b);

end Structoral;

Sub Program:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2_1 is
    Port ( a0 : in  STD_LOGIC;
           a1 : in  STD_LOGIC;
           s : in  STD_LOGIC;
           y : out  STD_LOGIC);
end mux_2_1;

architecture dataflow of mux_2_1 is
begin
y<=((not s) and a0) or (s and a1);
end dataflow;