GRAY-CODE DOWN COUNTER (Strucural)

Main Program:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity G_D_C is
    Port ( clk,clr,pr : in  STD_LOGIC;
           g: out  STD_LOGIC_VECTOR(3 downto 0));
end G_D_C;

architecture Structural of G_D_C is

component mjk is
Port ( clk,clr,pr,j,k : in  STD_LOGIC;
           q,qn : inout  STD_LOGIC);
end component;

component xor_d is
Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

signal q,qn:std_logic_vector(3 downto 0);


begin
u1:mjk port  map (clk,clr,pr,'1','1',q(0),qn(0));
u2:mjk port  map (qn(0),clr,pr,'1','1',q(1),qn(1));
u3:mjk port  map (qn(1),clr,pr,'1','1',q(2),qn(2));
u4:mjk port  map (qn(2),clr,pr,'1','1',q(3),qn(3));
u5:xor_d port map (q(0),q(1),g(0));
u6:xor_d port map (q(1),q(2),g(1));
u7:xor_d port map (q(2),q(3),g(2));
u8:xor_d port map ('0',q(3),g(3));
end Structural;

Sub Program:-

XOR:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity xor_d is
    Port ( a,b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end xor_d;

architecture Dataflow of xor_d is

begin
c<=a xor b;

end Dataflow;


JK FLIP-FLOP:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mjk is
    Port ( clk,clr,pr,j,k : in  STD_LOGIC;
           q,qn : inout  STD_LOGIC);
end mjk;

architecture Behavioral of mjk is
begin
process(clk)
begin
if pr='0' then q<='1';qn<='0';
elsif clr='0' then qn<='1';q<='0';
elsif clk' event and clk='1' then
elsif j=k then
if j='0' then q<=q;qn<=not q;
else qn<=q;q<=not q;
end if;
else
q<=j;qn<=not j;
end if;
end process;
end Behavioral;