CARRY LOOK AHEAD ADDER (Structural)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clas is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           s : out  STD_LOGIC_VECTOR (3 downto 0);
           ci : in  STD_LOGIC;C_out:out std_logic);
end clas;

architecture Behavioral of clas is

component ha is
port( a1 : in  STD_LOGIC;
      b1 : in  STD_LOGIC;
      s1 : out  STD_LOGIC;
  c1 : out  STD_LOGIC);
end component;

component cl is
 Port ( x : in  STD_LOGIC;
        y : in  STD_LOGIC;
        ci : in  STD_LOGIC;
        z : out  STD_LOGIC);
end component;

component xor_11 is
  Port ( a2: in  STD_LOGIC;
         b2: in  STD_LOGIC;
         c2: out STD_LOGIC);
end component;

  signal g,p,c:std_logic_vector(3 downto 0);
begin

u1:ha port map(a(0),b(0),p(0),g(0));
u2:ha port map(a(1),b(1),p(1),g(1));
u3:ha port map(a(2),b(2),p(2),g(2));
u4:ha port map(a(3),b(3),p(3),g(3));
u5:cl port map(p(0),g(0),ci,c(0));
u6:cl port map(p(1),g(1),c(0),c(1));
u7:cl port map(p(2),g(2),c(1),c(2));
u8:cl port map(p(3),g(3),c(2),c(3));
u9:xor_11 port map(p(0),ci,s(0));
u10:xor_11 port map(p(1),c(0),s(1));
u11:xor_11 port map(p(2),c(1),s(2));
u12:xor_11 port map(p(3),c(2),s(3));
C_out<=c(3);
end Behavioral;

Sub Program:-

Half Adder:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ha is

    Port ( a1 : in  STD_LOGIC;

           b1 : in  STD_LOGIC;

           s1 : out  STD_LOGIC;

           c1 : out  STD_LOGIC);

end ha;

architecture Behavioral of ha is

begin

s1<=a1 xor b1;

c1<=a1 and b1;

end Behavioral;

Carry Generation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity cl is

    Port ( x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           ci : in  STD_LOGIC;

           z : out  STD_LOGIC);

end cl;

architecture Behavioral of cl is

begin

z<=(x and ci) or y;

end Behavioral;

Xor:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity xor_11 is

    Port ( a2: in  STD_LOGIC;

           b2: in  STD_LOGIC;

           c2: out  STD_LOGIC);

end xor_11;

architecture Behavioral of xor_11 is

begin

c2<=a2 xor b2;

end Behavioral;