library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity muxx is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y :out STD_LOGIC);
end muxx;
architecture Dataflow of muxx is
begin
with s select
y<= x(0) when "00",
x(1)
when "01",
x(2)
when "10",
x(3)
when others;
end Dataflow;
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