Defining New Package in VHDL Programme

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;



package array_pack is
type array_7_7 is array (7 downto 0) of std_logic_vector(7 downto 0);
Type array_4_7 is array (3 downto 0) of std_logic_vector(6 downto 0);
Type array_4_4 is array (3 downto 0) of std_logic_vector(3 downto 0);
Type array_3_4 is array (2 downto 0) of std_logic_vector(3 downto 0);

end array_pack;