BCH Decoding

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
--use IEEE.STD_LOGIC_1164.ALL;


entity bch_decoding is
    Port ( data : in  STD_LOGIC_VECTOR (6 downto 0):="1101001";
 clk : in  STD_LOGIC ;
 m,clr : in  STD_LOGIC:='0';
           s_out : out  STD_LOGIC;
 outval : out  STD_LOGIC_VECTOR (6 downto 0));
end bch_decoding;

architecture Structoral of bch_decoding is
component d_ffs is
    Port ( d,clk : in  STD_LOGIC;
           q : inout  STD_LOGIC:='0';
           qn : inout  STD_LOGIC:='1');
end component;

component mux2x1 is
    Port ( a,b : in  STD_LOGIC;
           s : in  STD_LOGIC:='0';
           y : out  STD_LOGIC);
end component;

component xor_2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component and_2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component t_ff is
    Port ( t : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           q : inout  STD_LOGIC);
end component;

component detect100 is
    Port ( a,b,c,d,e : in  STD_LOGIC;
           y : out  STD_LOGIC);
end component;

signal q : STD_LOGIC_VECTOR (6 downto 0):="0000000";
signal qb : STD_LOGIC_VECTOR (2 downto 0):="000";
signal qq : STD_LOGIC_VECTOR (2 downto 0);
signal mx : STD_LOGIC_VECTOR (7 downto 1):="0000000";
signal a1o,x1o,x2o,f,a2o,cntrl_clk :  STD_LOGIC;

begin
x1: d_ffs port map (data(0),clk,q(0));
x2: mux2x1 port map (data(1),q(0),m,mx(1));
x3: d_ffs port map (mx(1),clk,q(1));
x4: mux2x1 port map (data(2),q(1),m,mx(2));
x5: d_ffs port map (mx(2),clk,q(2));
x6: mux2x1 port map (data(3),q(2),m,mx(3));
x7: d_ffs port map (mx(3),clk,q(3));
x8: mux2x1 port map (data(4),q(3),m,mx(4));
x9: d_ffs port map (mx(4),clk,q(4));
x10: mux2x1 port map (data(5),q(4),m,mx(5));
x11: d_ffs port map (mx(5),clk,q(5));
x12: mux2x1 port map (data(6),q(5),m,mx(6));
x13: d_ffs port map (mx(6),clk,q(6));
x15: mux2x1 port map (q(6),'0',clr,mx(7));
s_out<=mx(7);
x14: xor_2 port map (qb(2),mx(7),x1o);
--x15: and_2 port map (x1o,m,a1o);
x16: xor_2 port map (x1o,qb(0),x2o);
x17: d_ffs port map (x1o,clk,qb(0));
x18: d_ffs port map (x2o,clk,qb(1));
x19: d_ffs port map (qb(1),clk,qb(2));
--x20: cnt_3bit_str port map (m,clk,qq);
--
--x21: d_ffs port map (f,clk,qs(0));
--x22: d_ffs port map (qs(0),clk,qs(1));
--x23: d_ffs port map (qs(1),clk,qs(2));
--x24: d_ffs port map (qs(2),clk,qs(3));
--x25: d_ffs port map (qs(3),clk,qs(4));
--x26: d_ffs port map (qs(4),clk,qs(5));
--x27: d_ffs port map (qs(5),clk,qs(6));
outval(6 downto 4)<=qq;
outval(2 downto 0)<=qb;

 xclk: detect100 port map (clr,qb(2),qb(1),qb(0),clk,cntrl_clk);
xt1: t_ff port map ('1',clr,cntrl_clk,qq(0));
xt2: t_ff port map (qq(0),clr,cntrl_clk,qq(1));
xt4: and_2 port map (qq(0),qq(1),a2o);
xt3: t_ff port map (a2o,clr,cntrl_clk,qq(2));
end Structoral;