BCH Encoding in a Simple Way

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
--use IEEE.STD_LOGIC_1164.ALL;

entity p2s_str is
    Port ( data : in  STD_LOGIC_VECTOR (3 downto 0);
 clk : in  STD_LOGIC ;
 m : in  STD_LOGIC:='0';
           s_out : out  STD_LOGIC;
 outval : out  STD_LOGIC_VECTOR (6 downto 0));
end p2s_str;

architecture Structoral of p2s_str is
component d_ffs is
    Port ( d,clk : in  STD_LOGIC;
           q : inout  STD_LOGIC:='0';
           qn : inout  STD_LOGIC:='1');
end component;

component mux2x1 is
    Port ( a,b : in  STD_LOGIC;
           s : in  STD_LOGIC:='0';
           y : out  STD_LOGIC);
end component;

component xor_2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

component and_2 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end component;

signal q : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal qb : STD_LOGIC_VECTOR (2 downto 0):="000";
signal qs : STD_LOGIC_VECTOR (6 downto 0):="0000000";
signal mx : STD_LOGIC_VECTOR (3 downto 1):="000";
signal a1o,x1o,x2o,f :  STD_LOGIC;

begin

x1: d_ffs port map (data(0),clk,q(0));
x2: mux2x1 port map (data(1),q(0),m,mx(1));
x3: d_ffs port map (mx(1),clk,q(1));
x4: mux2x1 port map (data(2),q(1),m,mx(2));
x5: d_ffs port map (mx(2),clk,q(2));
x6: mux2x1 port map (data(3),q(2),m,mx(3));
x7: d_ffs port map (mx(3),clk,q(3));
s_out<=q(3);
x8: xor_2 port map (qb(2),q(3),x1o);
x9: and_2 port map (x1o,m,a1o);
x10: xor_2 port map (a1o,qb(0),x2o);
x11: d_ffs port map (a1o,clk,qb(0));
x12: d_ffs port map (x2o,clk,qb(1));
x13: d_ffs port map (qb(1),clk,qb(2));
x14: mux2x1 port map (qb(2),q(3),m,f);

x15: d_ffs port map (f,clk,qs(0));
x16: d_ffs port map (qs(0),clk,qs(1));
x17: d_ffs port map (qs(1),clk,qs(2));
x18: d_ffs port map (qs(2),clk,qs(3));
x19: d_ffs port map (qs(3),clk,qs(4));
x20: d_ffs port map (qs(4),clk,qs(5));
x21: d_ffs port map (qs(5),clk,qs(6));
outval(6 downto 3)<=data;
outval(2 downto 0)<=qb;
end Structoral;

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Mux 2 : 1 Sub Program:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2x1 is
    Port ( a,b : in  STD_LOGIC;
           s : in  STD_LOGIC:='0';
           y : out  STD_LOGIC);
end mux2x1;

architecture Behavioral of mux2x1 is

begin
--process(s)
--begin
--if s='0' then y<=a;
--else y<=b;
--end if;
--end process;
y<=(not s and a) or (s and b);

end Behavioral;

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D Flip-flop Sub Program:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity d_ffs is
    Port ( d,clk : in  STD_LOGIC;
           q : inout  STD_LOGIC:='0';
           qn : inout  STD_LOGIC:='1');
end d_ffs;

architecture Behavioral of d_ffs is

begin
process(clk)
begin
if clk='1' and clk' event then
q<=d;
qn<=not d;
else
q<=q;
qn<=qn;
end if;
end process;
end Behavioral;