SISO / PIPO Structural (4 Bit)

Main Program:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sipo_pipo is
    Port ( a,b,c,d,clk,m : in  STD_LOGIC;
           q : inout  STD_LOGIC_VECTOR (3 downto 0));
end sipo_pipo;

architecture Structural of sipo_pipo is
component not_1 is
    Port ( a : in  STD_LOGIC;
           b : out  STD_LOGIC);
end component;

component and_2xor_2blk is
    Port ( a,b,c,d : in  STD_LOGIC;
           e : out  STD_LOGIC);
end component;

component DFF is
    Port ( d,clk : in  STD_LOGIC;
           q,nq : inout  STD_LOGIC);
end component;
signal nm: std_logic;
signal s:std_logic_vector(0 to 3);
begin
u1:DFF port map (a,clk,q(0));
u2:DFF port map (s(0),clk,q(1));
u3:DFF port map (s(1),clk,q(2));
u4:DFF port map (s(2),clk,q(3));
u5:not_1 port map(m,nm);
u6:and_2xor_2blk port map(q(0),m,b,nm,s(0));
u7:and_2xor_2blk port map(q(1),m,c,nm,s(1));
u8:and_2xor_2blk port map(q(2),m,d,nm,s(2));
end Structural;

Sub Program:-

1. Not Gate:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity not_1 is
    Port ( a : in  STD_LOGIC;
           b : out  STD_LOGIC);
end not_1;

architecture Dataflow of not_1 is

begin
b<=not a;
end Dataflow;

2. Block For [(a and b) or (c and d)]:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity and_2xor_2blk is
    Port ( a,b,c,d : in  STD_LOGIC;
           e : out  STD_LOGIC);
end and_2xor_2blk;

architecture Dataflow of and_2xor_2blk is

begin
e<=(a and b) or (c and d);
end Dataflow;