Single Bit Manipulation ( Addition, Subtraction, Multiplication, Division )

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ALU is
port (a,b:in std_logic_vector(0 downto 0);
s0,s1:in std_logic;
f:out std_logic_vector(0 downto 0));
end ALU;

architecture behave of ALU is

begin
process(a,b)
begin
if s0='0' and s1='0' then
f<= a+b;
end if;
if s0='0' and s1='1' then
f<=a-b;
end if;
if s0='1' and s1='0' then
f<=a and b;
end if;
if s0='1' and s1='1' then
if a="1" and b="0" then f<="U";
else f<=a and b;
end if;
end if;
end process;

end behave;