-- For the sequence 1010
use IEEE.STD_LOGIC_1164.ALL;
entity seq_det is
Port ( input_pin : in STD_LOGIC;
clock_pulse : in STD_LOGIC;
clear_pin : in STD_LOGIC;
output_pin : out STD_LOGIC);
end seq_det;
architecture Behavioral of seq_det is
type state is (a,b,c,d,e);
signal present_state,next_state: state;
begin
clk_process: Process(clock_pulse)
begin
if clear_pin='0' then
present_state<=a;
else
if clock_pulse='1' and clock_pulse' event then
present_state<=next_state;
end if;
end if;
end process;
state_process: Process(present_state,input_pin)
begin
case present_state is
when a=>
if input_pin='1' then
next_state<=b;
else
next_state<=a;
end if;
when b=>
if input_pin='0' then
next_state<=c;
else
next_state<=b;
end if;
when c=>
if input_pin='1' then
next_state<=d;
else
next_state<=a;
end if;
when d=>
if input_pin='0' then
next_state<=e;
else
next_state<=b;
end if;
when e=>
if input_pin='0' then
next_state<=a;
else
next_state<=d;
end if;
end case;
end process;
output_process: Process(present_state)
begin
if present_state=e then
output_pin<='1';
else
output_pin<='0';
end if;
end process;
end Behavioral;
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