Program :-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FSM_mealy is
Port ( input_bit : in STD_LOGIC;
clock_pulse : in STD_LOGIC;
reset : in STD_LOGIC:='1';
output_bit : out STD_LOGIC);
end FSM_mealy;
architecture Behavioral of FSM_mealy is
type state is (A,B,C);
signal present_state,next_state: state;
begin
clk_process: Process(clock_pulse)
begin
if reset='0' then
present_state<=A;
else
if clock_pulse='1' and clock_pulse' event then
present_state<=next_state;
end if;
end if;
end process;
state_process: Process(present_state,input_bit)
begin
case present_state is
when A=>
if input_bit='1' then
next_state<=C;
else
next_state<=B;
end if;
when B=>
if input_bit='0' then
next_state<=B;
else
next_state<=A;
end if;
when C=>
if input_bit='1' then
next_state<=C;
else
next_state<=A;
end if;
end case;
end process;
output_process: Process(present_state,input_bit)
begin
if (present_state=B and input_bit='0') OR (present_state=C and input_bit='1') then
output_bit<='1';
else
output_bit<='0';
end if;
end process;
end Behavioral;
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