LOGIC GATES USING VERILOG HDL

NOT GATE

module andv(input a, output b);

assign b=~a;
endmodule


AND GATE

module andv(input a, b, output c);

assign c=a&b;
endmodule



NAND GATE

module andv(input a, b, output c);

assign c=~(a&b);
endmodule



OR GATE

module andv(input a, b, output c);

assign c=a|b;
endmodule



NOR GATE

module andv(input a, b, output c);

assign c=~(a|b);
endmodule



XOR GATE

module andv(input a, b, output c);

assign c=a^b;
endmodule



XNOR GATE

module andv(input a, b, output c);

assign c=~(a^b);
endmodule