library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comprtr is
Port ( a,b : in STD_LOGIC_VECTOR(2 downto 0);
e,l,g : out STD_LOGIC);
end comprtr;
architecture Dataflow of comprtr is
begin
e<='1' when a=b else '0';
l<='1' when a<b else '0';
g<='1' when a>b else '0';
end Dataflow;
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