Three Bit Comparator Using Single bit bit Comparators (Structural)

Main Program:-j

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Three_S_B_C is
    Port ( A : in  STD_LOGIC_VECTOR (2 downto 0);
           B : in  STD_LOGIC_VECTOR (2 downto 0);
           EN : in  STD_LOGIC;
           E : out  STD_LOGIC;
           L : out  STD_LOGIC;
           G : out  STD_LOGIC);
end Three_S_B_C;

architecture Strucural of Three_S_B_C is
component S_B_C is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           en : in  STD_LOGIC;
           e : out  STD_LOGIC;
           l : out  STD_LOGIC;
           g : out  STD_LOGIC);
end component;

component OR_22 is
    Port ( a : in  STD_LOGIC;
           b,c : in  STD_LOGIC;
           d : out  STD_LOGIC);
end component;

signal j,k,h:std_logic_vector(2 downto 0);

begin
u1:S_B_C port map(A(2),B(2),'1',j(2),k(2),h(2));
u2:S_B_C port map(A(1),B(1),j(2),j(1),k(1),h(1));
u3:S_B_C port map(A(0),B(0),j(1),E,k(0),h(0));
u4:OR_22 port map(k(2),k(1),k(0),L);
u5:OR_22 port map(h(2),h(1),h(0),G);
end Strucural;

Sub Program:-

1)Single Bit Comparator:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity S_B_C is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           en : in  STD_LOGIC;
           e : out  STD_LOGIC;
           l : out  STD_LOGIC;
           g : out  STD_LOGIC);
end S_B_C;

architecture Behavioral of S_B_C is

begin
process(a,b,en)
begin

if en='0' then e<='0';l<='0';g<='0';
elsif a=b then e<='1';l<='0';g<='0';
elsif a<b then e<='0';l<='1';g<='0';
else e<='0';l<='0';g<='1';
end if;

end process;
end Behavioral;

2)Or Gate:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OR_22 is
    Port ( a : in  STD_LOGIC;
           b,c : in  STD_LOGIC;
           d : out  STD_LOGIC);
end OR_22;

architecture Dataflow of OR_22 is

begin
d<=a or b or c;
end Dataflow;