4 BIT DOWN COUNTER (Structural)

Main Programe:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity upc is
    Port ( clk,clr,pr: in  STD_LOGIC;
           q : inout  STD_LOGIC_VECTOR (3 downto 0));
end upc;


architecture structoral of upc is

component mjk
port (clk,clr,pr,j,k :in std_logic;
                                q,qn:inout std_logic);
end component;

signal qs:STD_LOGIC_VECTOR (3 downto 0);

begin

u1:mjk port map (clk,clr,pr,'1','1',q(0),qs(0));
u2:mjk port map (qs(0),clr,pr,'1','1',q(1),qs(1));
u3:mjk port map (qs(1),clr,pr,'1','1',q(2),qs(2));
u4:mjk port map (qs(2),clr,pr,'1','1',q(3),qs(3));


end structoral;



Sub Programe:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mjk is
    Port ( clk,clr,pr,j,k : in  STD_LOGIC;
           q,qn : inout  STD_LOGIC);
end mjk;


architecture Behavioral of mjk is
begin
process(clk)
begin
if pr='0' then q<='1';qn<='0';
elsif clr='0' then qn<='1';q<='0';
elsif clk' event and clk='1' then
elsif j=k then
if j='0' then q<=q;qn<=not q;
else qn<=q;q<=not q;
end if;
else
q<=j;qn<=not j;
end if;
end process;
end Behavioral;