RIPPLE CARRY ADDER (Structural)

RIPPLE CARRY ADDER:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rca is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           Cin : in  STD_LOGIC;
           Cout : inout  STD_LOGIC;
           s : out  STD_LOGIC_VECTOR (3 downto 0));
end rca;

architecture Structural of rca is
component FA port(a,b,c:in std_logic;
sum,carry:out std_logic);
end component;
signal c: std_logic_vector(3 downto 1);
begin
u1:FA port map (a(0),b(0),Cin,s(0),c(1));
u2:FA port map (a(1),b(1),c(1),s(1),c(2));
u3:FA port map (a(2),b(2),c(2),s(2),c(3));
u4:FA port map (a(3),b(3),c(3),s(3),Cout);
end Structural;



FULL ADDER:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity FA is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           sum : out  STD_LOGIC;
           carry : out  STD_LOGIC);
end FA;
architecture dataflow of FA is
begin
sum<=a xor b xor c;
carry<=(a and b)or ((a xor b) and c);
end dataflow;