RAM

RAM

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ram1 is

    Port ( din : in  STD_LOGIC_VECTOR (7 downto 0);

           clk : in  STD_LOGIC;

           rw : in  bit;

           do : out  STD_LOGIC_VECTOR (7 downto 0));

end ram1;

architecture Behavioral of ram1 is

type ram1 is array (0 to 255) of std_logic_vector(7 downto 0);

signal addr1,addr2:std_logic_vector(7 downto 0) :="00000000";

signal data: ram1;

begin

process(clk,rw)

begin

if(clk'event and clk='1') then

if(rw = '1') then

data(conv_integer(addr1))<=din;

addr1<=addr1+"00000001";

elsif(rw = '0') then

do<=data(conv_integer(addr2));

addr2<=addr2+"00000001";

end if;

end if;

end process;

end Behavioral;