CARRY LOOK AHEAD ADDER Behavioral Model (VHDL)

Test Bench Program :-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_cla_behav IS
END tb_cla_behav;

ARCHITECTURE behavior OF tb_cla_behav IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT cla_behav
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         cin : IN  std_logic;
         cout : OUT  std_logic;
         sum : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal cin : std_logic := '0';

  --Outputs
   signal cout : std_logic;
   signal sum : std_logic_vector(3 downto 0);
   -- No clocks detected in port list. Replace <clock> below with
   -- appropriate port name


BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: cla_behav PORT MAP (
          a => a,
          b => b,
          cin => cin,
          cout => cout,
          sum => sum
        );



   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.

wait for 100 ns; a<="0001"; b<="0001";cin<='0';
      wait for 100 ns; a<="0101"; b<="1001";cin<='0';
      wait for 100 ns; a<="1001"; b<="1101";cin<='0';
      wait for 100 ns; a<="0111"; b<="1011";cin<='1';
      wait for 100 ns; a<="0101"; b<="1111";cin<='0';
      wait for 100 ns; a<="0011"; b<="1101";cin<='1';
      wait for 100 ns; a<="1000"; b<="0101";cin<='0';
      wait for 100 ns; a<="1101"; b<="1001";cin<='1';

      -- insert stimulus here

      wait;
   end process;


END;

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Carry Look Ahead Adder (  VHDL  )  :-

library ieee;
use ieee.std_logic_1164.all;

entity cla_behav is
Port(a,b:in std_logic_vector(3 downto 0);
cin: in std_logic;cout:out std_logic;
sum:out std_logic_vector(3 downto 0));
end cla_behav;

architecture Behavioral of cla_behav is
signal p,g:std_logic_vector(3 downto 0);
signal c:std_logic_vector(4 downto 0);
begin

sum_proc:process(a,b,c,cin)
begin
c(0)<=cin;
for i in 3 downto 0 loop
sum(i)<=a(i) xor b(i) xor c(i);
end loop;
end process;

generate_proc:process(a,b)
begin
for i in 3 downto 0 loop
g(i)<=a(i) and b(i);
end loop;
end process;

prop_proc:process(a,b)
begin
for i in 3 downto 0 loop
p(i)<=a(i) or b(i);
end loop;
end process;

carry_proc:process(p,g,c,cin)
begin
c(0)<=cin;
for i in 3 downto 0 loop
c(i+1)<=g(i) or (p(i) and c(i));
cout<=c(4);
end loop;
end process;

end Behavioral;