VHDL vs VERILOG

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Tuesday, 30 September 2014

GRAY-CODE DOWN COUNTER (Strucural)


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Posted by The Parent at 11:11:00 No comments:
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Monday, 29 September 2014

GRAY-CODE UP COUNTER (Strucural)


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Friday, 19 September 2014

4 BIT DOWN COUNTER (Structural)


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Popular Posts

  • 64 x 1 MULTIPLEXER using 8 x 1 multiplexer (Structural)
  • Mod 5 Up Counter (Verilog) with Test Fixture
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  • EVEN / ODD COUNTER (Behavioral)
  • Full Subtractor ( Verilog ) with Test Fixture
  • 3-Bit UP / DOWN Counter ( Structural ) with Test Bench Program
  • FULL ADDER using Two HALF ADDERS and One Or gate (STRUCTURAL)
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  • 64 x 1 MULTIPLEXER using 8 x 1 multiplexer (Structural) with the help of "GENERATE"
  • Demux 1 x 4 ( Verilog ) with Test Fixture

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