FUNCTION IMPLEMENTATION USING 2:1 MULTIPLEXERS (Structural)

THE FUNCTION HERE IS    1,3,5,6

Main Program:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fcn is
    Port ( a,b,c : in  STD_LOGIC;
           O : out  STD_LOGIC);
end fcn;

architecture Structoral of fcn is
component mux2 is
 Port ( a,b: in  STD_LOGIC;
           s : in  STD_LOGIC;
           y : out  STD_LOGIC);
end component;
signal  x:STD_LOGIC_VECTOR (5 downto 0);
begin
u1:mux2 port map ('0','1',c,x(0));
u2:mux2 port map ('0','1',c,x(1));
u3:mux2 port map ('0','1',c,x(2));
u4:mux2 port map ('1','0',c,x(3));
u5:mux2 port map (x(0),x(1),b,x(4));
u6:mux2 port map (x(2),x(3),b,x(5));
u7:mux2 port map (x(4),x(5),a,O);
end Structoral;


Program for 2:1 Mux (Dataflow) :-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2 is
    Port ( a,b: in  STD_LOGIC;
           s : in  STD_LOGIC;
           y : out  STD_LOGIC);
end mux2;

architecture dataflow of mux2 is

begin
y<=(a and (not s)) or (b and  s);

end dataflow;