AND Gate

AND GATE

DATA FLOW :-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and_2 is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end and_2;

architecture Dataflow of and_2 is

begin

C<= a and b;

end Dataflow;

BEHAVIORAL :-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and_2b is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end and_2b;

architecture Behavioral of and_2b is

begin

process(a,b)

begin

if a='1' and b='1' then c<='1';

else C<='0';

end if;

end process;

end Behavioral;

STRUCTURAL :-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity and_2s is

    Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end and_2s;

architecture Structural of and_2s is

Component and_2 is

 Port ( a : in  STD_LOGIC;

           b : in  STD_LOGIC;

           c : out  STD_LOGIC);

end component;

begin

and1:and_2 port map(a,b,c);

end Structural;