Procedure for Vhdl Stimulation in Xilinx

Procedure for Vhdl Stimulation in Xilinx

1.    The Xilinx design suit which version u has is opened. From the file menu ‘new project’ is selected.

2.    In new project wizard name of project is mentioned. Then in new project wizard device properties ISE simulator is selected and then finish is chosen.

3.    In project, new source is selection type, ‘vhdl module’ is selected. And file name is given. Then design or type your program and saved.

4.    Syntax is verified using the ‘check syntax’ option in process navigator bar.

5.    Simulation is done by selecting ‘behavioral simulation’ from ‘source window’ and the corresponding file is selected.

6.    In project, new source is selection type, ‘test bench wave form’ is selected. And file name is given. Then inputs are given and saved.

7.    Then click on ‘simulation’

8.    Verify the output waveform.