* Data will be shown at out, from which address we are selected.
* Store the value to memory when we give the 'Read_Write' pin , a high value.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity RAM_16_x_1024 is
Port ( Data_in : in STD_LOGIC_VECTOR (15 downto 0);
Address : in STD_LOGIC_VECTOR (9 downto 0):="0000000000";
Read_Write,clk : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (15 downto 0));
end RAM_16_x_1024;
architecture Behavioral of RAM_16_x_1024 is
type ramm is array(2**(Address' length)-1 downto 0) of std_logic_vector(2**(Data_in' length)-1 downto 0);
signal temp:ramm;
begin
process(clk,Data_in)
begin
if clk='0' and clk'event then
if Read_Write='1' then
temp(conv_integer(Address))<=Data_in;
end if;
end if;
end process;
Data_out<=temp(conv_integer(Address));
end Behavioral;
* Store the value to memory when we give the 'Read_Write' pin , a high value.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity RAM_16_x_1024 is
Port ( Data_in : in STD_LOGIC_VECTOR (15 downto 0);
Address : in STD_LOGIC_VECTOR (9 downto 0):="0000000000";
Read_Write,clk : in STD_LOGIC;
Data_out : out STD_LOGIC_VECTOR (15 downto 0));
end RAM_16_x_1024;
architecture Behavioral of RAM_16_x_1024 is
type ramm is array(2**(Address' length)-1 downto 0) of std_logic_vector(2**(Data_in' length)-1 downto 0);
signal temp:ramm;
begin
process(clk,Data_in)
begin
if clk='0' and clk'event then
if Read_Write='1' then
temp(conv_integer(Address))<=Data_in;
end if;
end if;
end process;
Data_out<=temp(conv_integer(Address));
end Behavioral;
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